1. Field of the Invention
This disclosure relates generally to computer processors, and particularly to mitigation of dependencies in the instruction stream, including so-called “evil twin” conditions.
2. Description of the Related Art
In some computer instruction set architectures (ISAs), instructions may address portions of a register. Such architectures may, as a result, exhibit dependency conditions, including what can be referred to as an “evil twin” condition in the context of an architecture that allows addressing of single-precision portions of a double-precision “aliased” register pair.
An evil twin condition may arise, for example, in a processor implementing the SPARC ISA. The SPARC ISA allows a logical 64-bit floating-point (FP) register to be accessed as either one double-precision (DP) register or as two single-precision (SP) registers. The SPARC ISA provides SP FP instructions that specify SP source and destination registers as well as DP FP instructions that specify DP source and destination registers. Performance penalties have arisen when an application program uses both SP FP instructions and DP FP instructions within the same code region. Specifically, a performance penalty may exist where a DP FP instruction that has, as its source(s), one or more DP FP register(s) that is (are) the destination(s) of one or more preceding SP FP instructions that are still being executed by the processor (i.e. they have not yet retired). One situation in which this condition may arise is when a compiler cannot ascertain that DP FP data is stored in a 64-bit aligned memory location. The compiler then uses two SP FP loads to read the two halves of the DP data before performing computation on the data using a DP FP instruction.
Dependencies such as evil twin conditions are problematic for processor performance.